Initial Frequency Preset Technique for Fast Locking Fractional-N PLL Synthesizers

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures KVCO on a chip, computes the VCO’s target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than 12.8 ms over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.