Physical design automation of transistor networks

Integrated circuits implemented with traditional standard cell approaches use a limited set of cells available in a library, created in advance, to generate its layout. It breaks complexity but frequently generates circuits with more transistors (due to the reduced numbers of functions and sizes available), more area, higher delays and more power consumption (mainly due to static power consumption, which is proportional to the number of transistors) than its potential. Many approaches have been attempted to improve this scenario at layout level: cell synthesis tools (to speed up the turnaround time of new cells), library-free layout synthesis and full custom layouts. We present in this paper a review of the methodologies and algorithms used in prior works for transistor-level layout synthesis, and especially recent ones targeting technologies beyond 65 nm.