Advanced Database Set Reduction Through Layout Trimming Technique for Fast Post Layout Simulation

Huge parasitic extraction runtime is always proportional to the size of the design database and is one of the gating factors in the product design cycle. There is currently no comprehensive solution for actual selected partial parasitic extraction for what-if analysis or if the design of concern is dispersed across several domains in the System on Chip (SoC) with crucial timing specification in between. The main idea of this study is to look for a real layout size reduction solution for fast electrical change order (ECO) with full layout to schematic cross referenced to allow seamless back annotation during post-layout simulation as well as preserving the important post layout parameters. The proposed technique allowed for real database reduction prior to layout database processing and parasitic extraction, significantly reducing the size of the database and the computation time needed to complete the parasitic extraction flow. The whole database set and a trimmed version of the database are compared in the experimental results employing Silterra 0.18-m technology design. Parasitic extraction solution is using Mentor Graphics Calibre platform which consists of layout versus schematic (LVS), and parasitic extraction (PEX xRC).