Study on failure mechanism caused by voltage leap of SGT-MOSFET during UIS testing

During the unclamped inductive load switching (UIS) testing or system application of power SGT-MOSFET, it is found that the step leap of drain voltage occurs during clamping at high avalanche current. This voltage leap eventually leads to the failure of device. In this paper, the structural modeling and simulation analysis of the related products reveal that the drain voltage leap is ultimately caused by the turn-off of the triggered npn transistor. By comparing the static with the dynamic avalanche characteristic curves, it is found that the robustness of SGT-MOSFET during self-clamping is limited by the different differential resistance branches on the static avalanche breakdown curve. It is pointed out that the negative differential resistance branch is the primary cause of the parasitic npn transistors triggering. When the device structure parameters are determined, the current that causes the parasitic transistor to be triggered has a certain value, so the higher the turn-off current is, the longer the duration of voltage leap during clamping is. Theoretically, the avalanche ruggedness of SGT-MOSFET can be estimated by the snapback current on the static avalanche breakdown curve. • The NDR is the primary cause of the parasitic transistor triggering. • The change of the number of triggered parasitic npn transistors causes the drain voltage waveform of SGT-MOSFET during UIS to appear multiple step leap. • The ruggedness of SGT-MOSFET is limited by the different differential resistance branches on the static avalanche breakdown curve. • The avalanche ruggedness of SGT-MOSFETs can be theoretically predicted by the snapback current.