Tathagata Srimani,Gage Hills,C.L. Lau,Max M. Shulaker
出处
期刊:Symposium on VLSI Technology日期:2019-06-01卷期号:: T24-T25被引量:17
标识
DOI:10.23919/vlsit.2019.8776514
摘要
Here we show a hardware prototype of a monolithic three-dimensional (3D) imaging system that integrates computing layers directly in the back-end-of-line (BEOL) of a conventional silicon imager. Such systems can transform imager output from raw pixel data to highly processed information. To realize our imager, we fabricate 3 vertical circuit layers directly on top of each other: a bottom layer of silicon pixels followed by two layers of CMOS carbon nanotube FETs (CNFETs) (comprising 2,784 CNFETs) that perform in-situ edge detection in real-time, before storing data in memory. This approach promises to enable image classification systems with improved nrocessing latencies.