Implementation of a Reduced Latency MAC Sublayer for High-Speed Ethernet Applications

Southwest Research Institute (SwRI) recently developed a new high-speed data link with low latency and data prioritization as part of the Data Line Control subsystem. The project team worked on designing and testing the hardware and FPGA IP to provide the lowest latency possible for the current specification while maintaining the reliability of the PHY Ethernet sublayer. The data link consists of a single Advanced Extensible Interface (AXI) into two custom Media Access Control (MAC) blocks on an FPGA. The MACs each control separate 1 Gb Physical Layer Transfer ICs with a max throughput of 2 gigabits. The AXI is routed into the MAC IP that prioritizes data and transmits to the PHY at a latency of <50ns. This paper will focus on the design concepts, the functionality of the data link, lessons learned, and how the connection can be developed for different high-speed Ethernet applications in the future.