Highest Quality and Repeatability for Single Wafer 150mm SiC CMP Designed for High Volume Manufacturing

薄脆饼 化学机械平面化 材料科学 抛光 磨料 模具准备 晶圆回磨 复合材料 光电子学 晶片切割
作者
Sean Yu,Hu Ji,Long Long Xu,Mike Liu,Eulia Liu,John Givens,Jamie Leighton
出处
期刊:Materials Science Forum 卷期号:1062: 229-234 被引量:1
标识
DOI:10.4028/p-a66637
摘要

Silicon Carbide (SiC) provides excellent characteristics such as superior thermal conductivity, high carrier mobility and extreme chemical stability in comparison with those of Silicon (Si). SiC is already showing significant device performance benefits in power devices, high performance communication, and LED lighting. However, SiC presents many challenges for wafer surface treatment because of its high hardness and remarkable chemical inertness. Today, mechanical polishing techniques on industrial batch CMP tools are the predominant methods for SiC wafer surface treatment, but material removal rate (MRR), surface defects and wafer flatness control are reaching fundamental limits with increasing wafer diameter. Batch processing typically results in a higher amount of surface scratches and defects, higher wafer to wafer variability, and higher wafer breakage rates. A unique single wafer chemical mechanical polishing (CMP) technique on 150mm n-doped, 4° off-axis, single crystal, 4H-SiC wafers was developed to create a virtually defect-free surface. A polishing head has been designed to manipulate polishing pressures at various zones of the wafer. This capability can modulate the removal thickness at each region on the wafer surface, resulting in a highly uniform wafer profile. Additionally, a CMP slurry has been formulated to maximize MRR from 2μm/hr to over 8.5μm/hr. Potassium permanganate has been selected as an oxidant and aluminum oxide particles as the abrasive. The oxidant concentration and abrasive content along with slurry pH level have also been optimized for ideal chemical and mechanical activity. Scratch-free wafer surfaces are observed with atomic force microscopy (AFM) and bright field (BF) and dark field (DF) inspection techniques. Roughness on the Si face is reduced to below 0.08nm. Total length of surface scratches was reduced to 10mm or less. Industrial metrics of wafer flatness, including total thickness variation (TTV) and local thickness variation (LTV) are modulated and improved. A test run completed on 25-wafers shows an overall 31% improvement of TTV post CMP process.

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