硅光子学
中间层
CMOS芯片
光子学
互连
材料科学
带宽(计算)
光电子学
硅
光电探测器
电气工程
计算机科学
电子工程
工程类
电信
纳米技术
蚀刻(微加工)
图层(电子)
作者
Lieve Bogaerts,Zaid El-Mekki,Stefaan Van Huylenbroeck,P. Nolmans,Nicolas Pantano,Xiao Wei Sun,Michal Rakowski,Dimitrios Velenis,Peter Verheyen,Sadhishkumar Balakrishnan,Peter De Heyn,Bradley Snyder,Yoojin Ban,S. A. Srinivasan,S. Lardenois,J. De Coster,Mikael Detalle,P. Absil,Andy Miller,Marianna Pantouvaki,Joris Van Campenhout
标识
DOI:10.1109/s3s.2018.8640164
摘要
The growing demand for I/O bandwidth in highperformance applications, such as datacenter switches and HPC nodes, drives the need for on-package integration of Optical I/O modules with the host CMOS ICs [1]. Silicon Photonics (SiPh) is a prime technology platform to realize multi-Tb/s hybrid CMOS-SiPh modules for 1m-500m+ optical interconnect distances [2]. Such Optical I/O modules require interfaces for dense, high-speed electrical I/O and low-noise power and ground delivery, which can be enabled by the integration of through-silicon vias (TSV) into the SiPh platform. Here, we describe challenges and results for 10μm x 100μm TSV-middle integration into a 300mm SiPh interposer platform. TSVs with low RF loss up to 50GHz are demonstrated along with low SiPh waveguide losses and high-performance Ge photodetectors.
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