Opportunities in 3-D stacked CMOS transistors

3-D stacked CMOS transistors offer an opportunity to enable further standard cell and SRAM scaling, making them a promising transistor architecture to extend Moore's law. We review state-of-the-art approaches for achieving 3-D CMOS stacking. The sequential approach is highlighted by fabricating Ge PMOS stacked via layer transfer on top of Si NMOS, and self-aligned approach is demonstrated by simultaneously fabricated NMOS-on-PMOS multi-nanoribbon Si transistors. Both approaches showcase a well-balanced CMOS inverter built from transistors in top and bottom device layers.