Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern

Advances in integrated circuit process technology have led to new defect mechanisms, and weak resistive defects in standard cells have received attention in addition to traditional defect types. Such defects are categorized as small delay defects that affect the reliability of a circuit. The delay introduced by such defects overlaps with the delay distribution resulting from the random process variation. Combining the results of the theoretical analysis, we propose a test method to improve the probability of detecting cell internal weak defects in the presence of process variation. The path with the minimum logic depth is selected as the test path, and the test pattern that enhanced the small delay of weak defects is paired with the test path. The improvements in defect detection probability over traditional tests are demonstrated on the ISCAS89 benchmark circuits. The results show that the proposed method provides an order of magnitude improvement in the probability of detecting cell internal weak defects.