A GPGPU microarchitecture supports multi-path execution and branch compaction

GPGPU supports high-performance execution due to its powerful parallel computing capability. However, when meets branch divergent, only a subset of its SIMD lanes could issue and execute thread, which leads to the degradation of performance. Current branch compaction mechanisms such as thread block compaction (TBC) and SIMD lane permutation (SLP) can effectively alleviate this phenomenon, but none of these mechanisms support interleave execution of multiple control flows generated by branch divergent, which limits the improvement of thread-level parallelism (TLP) and performance. In this paper we propose a new microarchitecture that supports multi-path interleave execution and branch compaction at the same time. Our microarchitecture records the information of both two control flows into the same entry. Then two execution masks are used to provide executable information of interleaved control flows. We use a set of workloads with massive branch divergent to evaluate our microarchitecture. The result demonstrates that our design outperforms baseline, TBC and SLP, with a harmonic mean of 4.7%, 3.4% and 2.3%.