7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur

A ring oscillator (RO) based phase-locked loop (PLL) is a promising candidate for multilane communication applications due to its small footprint, wide frequency tuning range, inherent multi-phase generation and frequency-pulling resilience. However, the RO suffers from inferior phase noise (PN) and a high flicker-noise corner, limiting the overall jitter performance. While the injection-locked clock multiplier (ILCM) [1] and the multiplying delay-locked loop (MDLL) [2] can effectively suppress the RO PN through the phase-realignment mechanism, the reference (REF) spur increases significantly due to the imperfect alignment timing, thus imposing a complex calibration. Type-I topology with a sampling phase detector or filter is attractive due to the inherent stability under high loop bandwidth (BW) [3], while the high phase detection gain (K PD ) also helps to suppress the in-band noise. Still, the REF frequency limits the achievable phase margin (PM) bound of the sampling PLL, e.g., a maximum of 45° for a 1/4 f REF unit-gain BW [3], while increasing the REF frequency increases the crystal oscillator cost. Although the insertion of the REF frequency multiplier before the main PLL can relieve the BW-stability tradeoff, the digital background calibration typically requires an excessively long settling time eventually reaching milliseconds [4]. Alternatively, cascading the closed-loop sampling delay-locked loop [5] or the open-loop feedforward PN cancellation block [6] after the main PLL can lead to a large PN filtering effect. Yet, the additional high-frequency voltage-controlled delay line results high power consumption and the open-loop feedforward PN cancellation scheme requires off-chip gain calibration.