Architecture implications of pads as a scarce resource

电迁移 噪音(视频) 电压 缩放比例 炸薯条 计算机科学 功率(物理) 电子工程 带宽(计算) 电气工程 工程类 电信 物理 图像(数学) 人工智能 量子力学 数学 几何学
作者
Runjie Zhang,Ke Wang,Brett H. Meyer,Mircea R. Stan,Kevin Skadron
出处
期刊:Computer architecture news [Association for Computing Machinery]
卷期号:42 (3): 373-384 被引量:15
标识
DOI:10.1145/2678373.2665728
摘要

Due to non-ideal technology scaling, delivering a stable supply voltage is increasingly challenging. Furthermore, com- petition for limited chip interface resources (i.e., C4 pads) between power supply and I/O, and the loss of such resources to electromigration, means that constructing a power deliverynetwork (PDN) that satisfies noise margins without compromising performance is and will remain a critical problem for architects and circuit designers alike. Simple guardbanding will no longer work, as the consequent performance penalty will grow with technology scaling In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation techniques, and the consequent implications of electromigration-induced PDN pad failure. Our simulations demonstrate that, despite their integral role in the PDN, power/ground pads can be aggressively reduced (by conversion into I/O pads) to their electromigration limit with minimal performance impact from extra voltage noise - provided the system implements a suitable noise-mitigation strategy. The key observation is that even though reducing power/ground pads significantly increases the number of voltage emergencies, the average noise amplitude increase is small. Overall, we can triple I/O bandwidth while maintaining target lifetimes and incurring only 1.5% slowdown
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