Optimized Wafer Edge Condition in Lithographic Process For Peeling Defect Reduction

As technology develops and transistor size keeps shrinking, it is critical to define high-resolution patterns in integrated chip manufacturing by optimizing bevel rinse condition of lithography processes. The presence of multiple organic film stacks requires corresponding complicated etching processes and may lead to unwanted damages in the post removal. The wafer edge and bevel just need to be protected since wafer processing issues can be induced by bevel profile, and the etching could change its shape while the wafer bevel is usually naked to plasma. This paper presented an un-health rinse condition at the bevel area that leaked to the striping of hard mask oxide and became the peeling source. The oxide film cannot be totally removed at the etch process and is easy to peel off at the bevel area. With step-by-step investigation, the peeling source occurred in photo step and is enhanced after etch process. A series of experiments were conducted to find out the optimized bevel rinse condition. With the solution, the defect chart showed that the peeling source defect level dropped down obviously.