横杆开关
计算机科学
冯·诺依曼建筑
电阻随机存取存储器
内存处理
并行计算
瓶颈
加法器
非易失性存储器
建筑
内存体系结构
计算机体系结构
计算机硬件
计算科学
嵌入式系统
电气工程
延迟(音频)
电压
工程类
搜索引擎
艺术
视觉艺术
Web搜索查询
电信
情报检索
按示例查询
操作系统
作者
Bing Chen,Fuxi Cai,Jiantao Zhou,Wen Ma,Patrick Sheridan,Wei Lü
标识
DOI:10.1109/iedm.2015.7409720
摘要
To solve the "big data" problems that are hindered by the Von Neumann bottleneck and semiconductor device scaling limitation, a new efficient in-memory computing architecture based on crossbar array is developed. The corresponding basic operation principles and design rules are proposed and verified using emerging nonvolatile devices such as very low-power resistive random access memory (RRAM). To prove the computing architecture, we demonstrate a parallel 1-bit full adder (FA) both by experiment and simulation. A 4-bit multiplier (Mult.) is further obtained by a programed 2-bit Mult. and 2-bit FA.
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