Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices

Dipole- first gate stack is demonstrated as a scalable, thermal budget flexible and wide/fine-tunable multi- Vt solution for 3D integrated gate-all-around nanosheet devices. Whereas a dipole-forming shifter is deposited on high-k in “dipole-last” scheme, the shifter is deposited directly on SiO 2 interface layer (IL) in “dipole-first”. This enables to (1) reduce the thermal budget of gate stack process and (2) provide a larger Vt shift than the dipole-last scheme. Zero-thickness dipole-first with ~350 mV EWF shift is demonstrated by using LaO with drive-in anneal and removal. LaO dipole-first shows limited mobility degradation, however, some penalties are seen in Tinv, Dit and gate leakage current. A novel dipole material provides a fine-tunable dipole-first stack with improved EOT, gate leakage current and uniformity as compared to LaO.