Investigating the Effect of the DC Block Capacitor on Residual Current in a System-Level ESD-Protected Circuit

This work aims to delve into the DC (Direct Current) block capacitor effect on the residual current in a system-level ESD (Electrostatic Discharge)-protected circuit. First, the relation between the residual current and DC block capacitor value has been introduced by applying two theoretical methods: circuit analysis and frequency response analysis. Then, a test circuit with 12 different DC block capacitors (0.5pF to 10nF) is employed to extract simulation and measurement results. Both SPICE (Simulation Program with Integrated Circuits Emphasis) transient analysis by simulating the IEC 61000-4-2 waveform and the measurement test setup by applying a system-level ESD simulator reveals that a test circuit with the lowest DC block capacitor is more unsusceptible than others. As a result, decreasing the value of the DC block capacitor can help reduce the destructive effect of ESD.