逐次逼近ADC
积分器
过采样
噪声整形
CMOS芯片
电子工程
无损压缩
计算机科学
噪音(视频)
比较器
数学
控制理论(社会学)
电气工程
电压
工程类
算法
带宽(计算)
电信
人工智能
数据压缩
控制(管理)
图像(数学)
作者
Pinyun Yi,Yuhua Liang,Shubin Liu,Nuo Xu,Liang Fang,Yue Hao
出处
期刊:IEEE Transactions on Circuits and Systems Ii-express Briefs
[Institute of Electrical and Electronics Engineers]
日期:2021-10-20
卷期号:69 (3): 859-863
被引量:60
标识
DOI:10.1109/tcsii.2021.3121245
摘要
This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting the cascaded integrator feed-forward (CIFF) structure, the proposed architecture employs unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function. Since to the lossless residue extraction and summation, it exhibits high efficiency in realizing the strong noise-shaping (NS) effect. Fabricated in a 65-nm 1P9M CMOS technology, the prototype NS-SAR ADC consumes $113.02~\mu \text{W}$ when operating at a 1.2-V supply voltage and at a sampling rate of 20 MS/s. It achieves a peak Schreier FoM of 176.73 dB with a signal to noise and distortion-ratio (SNDR) of 79.3 dB at an oversampling ratio (OSR) of 16.
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