德拉姆
泄漏(经济)
动态随机存取存储器
材料科学
数据保留
晶体管
电容
存水弯(水管)
电容器
光电子学
电气工程
存储单元
收缩率
电子工程
复合材料
工程类
化学
电压
半导体存储器
电极
物理化学
环境工程
经济
宏观经济学
作者
Dong‐Guk Han,Hoonchang Yang,Jinyeong Hwang,Jin-Seon Kim,Kyoungrak Cho,In-Hyun Nam,Daesun Kim,Beomseop Lee,Sung-Soo Yim,Heeil Hong,Joo‐Young Lee
出处
期刊:Proceedings
日期:2022-10-26
标识
DOI:10.31399/asm.cp.istfa2022p0362
摘要
Abstract DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.
科研通智能强力驱动
Strongly Powered by AbleSci AI