Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate

This chapter discusses the need to scale down the transistors incessantly to sustain the smart revolution in this era of Internet-of-Things and its implication on the behavior of transistors as switches. Although transistor scaling leads to an increase in the packing density, ultra-fast operation, and low cost, concurrently, its characteristics as a switch degrades significantly, deviating far from an ideal switch, owing to the various short channel effects. These short channel effects that originate when the channel length becomes comparable to the width of the depletion region at the source/channel and channel/drain interface, including carrier velocity saturation, channel charge sharing, drain-induced barrier lowering, gate-induced drain leakage, hot carrier injection, etc., are discussed in detail in this chapter. After discussing these short channel effects, various ways to mitigate these short channel effects at different levels of abstraction, such as channel engineering, multigate architecture, alternate conduction mechanisms, are also discussed.