High-Performance CMOS TIA for Data Center Optical Interconnects

An overview of Silicon Photonics and SiGe bipolar TIAs are presented for data center links. CMOS inverter-based TIA circuit topologies for high-bandwidth, low-noise, low-power, and high-linearity are discussed in brief. A design methodology to achieve the best overall receiver sensitivity is presented for a standalone TIA and a TIA codesigned with a DSP. The codesigned TIA methodology is validated using a 106.25 Gbps PAM-4 TIA prototype. Designed in a 16 nm FinFET CMOS process, the TIA with a transimpedance gain of 76 dBΩ has a range of 16 dBΩ. The TIA consumes 103.6 mW, has a -3 dB bandwidth of 18.4 GHz, an input-referred noise of 1.58 µA, and a noise density of 9.7 pA/√Hz.