Transistor Compact Model Based On Gradient Constrainted Convolution Neural Network

In semiconductor research, the characteristic curves of analog devices under different combinations of process and device structure parameters are very important. Traditional TCAD simulation plays a very important role, but building a compact model based on quantum physics requires a lot of effort and time, and shows relatively weak technical adaptability. The derivative of the model output may also lose continuity. In order to solve these problems, this work proposes a gradient supervised convolution neural network model with adaptive dynamic adjustment of learning rate. It is employed to model the I-V characteristics of GAA and PLANAR devices and achieves the continuity of higher-order derivatives. In addition, this work designs effective data preprocessing and new weighted loss function to enhance model expressivity. The I-V curves and physical verification of GAA and PLANAR devices by the proposed model show that the model can obtain high-precision fitting and achieve high-order differentiable continuity.