Gate/Drain Coupled Barrier Lowering Effect and Negative Threshold Voltage Shift in Schottky-Type p-GaN Gate HEMT

To assess GaN power transistors' capability to maintain a decent E-mode operation, ${V}_{\text {th}}$ at high ${V}_{\text {DS}}$ is measured for Schottky-type p-GaN gate HEMT, and an excessive negative ${V}_{\text {th}}$ shift is observed. With ${V}_{\text {DS}} =1$ V, ${V}_{\text {th}}$ is around 1.3 V at ${I}_{\text {D}} =1$ mA, but ${V}_{\text {th}}$ drops by ~0.6 V when measured at a high ${V}_{\text {DS}}$ of 100 V. In comparison, ohmic-type p-GaN gate HEMT only shows a negligible ${V}_{\text {th}}$ shift up to ${V}_{\text {DS}} =100$ V. A gate/drain coupled barrier lowering (GDCBL) effect is proposed to explain the appreciable ${V}_{\text {th}}$ shift in Schottky-type p-GaN gate HEMT. Upon high ${V}_{\text {DS}}$ , the potential of the floating p-GaN layer is raised by the drain through the capacitive coupling between p-GaN and drain ( ${C}_{\text {DP}}$ ). The positive potential of the p-GaN layer then lowers the energy barrier along the gated channel, resulting in a reduced ${V}_{\text {th}}$ . This effect is confirmed by the dependence of measured negative ${V}_{\text {th}}$ shift upon the property of gate/p-GaN contact and also by the numerical simulations that reveal the change in band diagrams upon high ${V}_{\text {DS}}$ .