Investigating a defect width identification based on half-peak width for LDC-based eddy current testing

The eddy current testing (ECT) technology based on the Inductance-to-Digital Converter (LDC) has the advantages of low power consumption and simple signal conditioning circuitry, which contributes to the miniaturisation of the instrument and low power consumption design. Existing defect identification methods primarily focus on the conventional Analog-to-Digital Converter (ADC)-based ECT. These methods rely on complex analytical models to analyze the phase and amplitude information of voltage signal. However, these approaches do not apply to the LDC-based ECT. The paper proposes a method to identify defects employing the Rp-Inductance 2D plane, and use the half-peak width of the inductance signal to evaluate the defect width for symmetric slots. Using finite element simulation and experimental verification, the half-peak widths of the inductive signal wave crests at the defects are the same for the four slots with 1 mm width and different depths on the aluminum specimen; for four wire-cut slots with 4 mm depth and different widths, the half-peak widths are positively correlated with the defect widths. These experimental results demonstrate that the relationship between crack width, wave crest, and half-peak width can serve as the foundation for width identification and classification. This also offers a fresh perspective for further quantifying crack widths.