Design of Accelerator for MobileNet Convolutional Neural Network Based on FPGA

MobileNet is a convolutional neural network with high recognition rate, less calculation and parameters, which is very suitable for embedded devices. This work designs a special parallelization acceleration unit for MobileNet architecture. On this basis, the whole operation of the architecture is realized in the form of reuse. Secondly, through configurable design, a depthwise separable convolution layer can support multilayer operations with different configurations. Finally, this work optimizes the timing of the architecture and implements pipeline operations between convolutional layers. In this way, the real-time performance of the system and the resource utilization of hardware acceleration unit can be improved. The maximum frame rate is 5.52fps and the power consumption of the system is 2.149W, while the design is run on the ZynqXC7z045 platform with a 100MHz work clock frequency.