32 × 64 SPAD Imager Using 2-bit In-Pixel Stack-Based Memory for Low-Light Imaging

This article presents a high-detection rate single-photon avalanche diode (SPAD) imaging chip designed for photon-sensing applications. The test chip includes two essential design techniques: passive quenching active clock-drive reset (PQACR) to maximize the detection window and in- pixel stack-based memory (IPSM) to reduce the effective dead time. PQACR architecture achieves 97.5% coverage detection window with minimal photon loss using a single transistor, while the IPSM architecture reduces the effective dead time from 33 to 22 ns with 28 transistors, overcoming the dead-time limitation issue in photon-counting designs. A test chip with a ${32} \times {64}$ array has been fabricated in Taiwan semiconductor manufacturing company (TSMC) 0.18- $\mu \text{m}$ HV CMOS process. Experimental results demonstrate that the proposed chip achieves less dead time and photon loss, making it well suited for high-speed and low-light imaging applications.