Process challenges of the STRASS technique to increase the electron mobility in advanced FD-SOI nMOSFETs

Abstract To improve the I on /I off performance of transistors, it is crucial to significantly increase the charge carrier mobility in the channels of field-effect transistors. Tensile stress/strain is known to improve the electron mobility in the channels of nMOSFETs. This paper focuses on the STRASS (Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI) process for introducing tensile stress into the silicon channel of the next-generation n-type Fully Depleted Silicon-On-Insulator (FD-SOI) devices. This technique is challenging, especially for very thin silicon film channels (e.g., less than 10 nm), where the controlled creation of a buried amorphous layer by ion implantation is difficult. By carefully optimizing the individual process steps of the STRASS technique, we have achieved the transfer of up to 1.6 GPa of tensile stress into the silicon of blanket SOI wafers. Graphical abstract