Low‐power column counter with a logical‐shift algorithm for CMOS image sensors

The authors propose a column counter that uses a logical-shift algorithm in column-parallel single-slope ADCs for low-power CMOS image sensors. The proposed column counter lowers power consumption by reducing the amount of internal toggling nodes and parasitic capacitance. Simulation results showed a 32% reduction in power consumption and a 60% reduction in the power-delay product compared to a conventional up/down counter.