Power-efficient network-on-chip design by partial topology reconfiguration

Network topology greatly affects the energy consumption, performance, cost, and design time/effort of the Networks-on-Chip (NoC) employed in today's Systems-on-Chip (SoCs). Most existing NoC architectures adopt either standard regular or customized topologies. In this chapter, a new architecture is proposed which is capable to establish virtual adaptive links between non-adjacent network nodes of a regular mesh-based NoC to shorten the distance between them. These virtual adaptive links are short-cut paths created by bypassing the intermediate routers along the path. The proposed adaptive links use part of the bit-width of the regular mesh links to create short-cut paths, so they customized irregular topologies on a regular mesh while imposing negligible area overhead. Consequently, the proposed architecture benefits from the regularity, desirable design time/effort, and scalability of a regular mesh, as well as the superior power/performance of customized irregular topologies. The reconfigurability, by which the adaptive links can be set up or torn down dynamically at run time, is the key advantage of the proposed architecture over the existing topology customization methods. The adaptive links can be constructed either at run time or design time. The run-time mechanism of creating virtual adaptive links consists of two light and fast procedures: on-chip traffic monitoring and virtual link reconfiguration. The former gathers network traffic statistics during a given time interval and the latter reconfigures adaptive link paths based on the current on-chip traffic pattern and in favor of heavy traffic flows. Experimental results show significant improvements can be achieved by the proposed architecture over some state-of-the-art NoC designs in terms of flexibility and energy-efficiency, with negligible area overhead.