A Source Segmented LDMOS Structure for Improving Single Event Burnout Tolerance Based on High-Voltage BCD Process

The Lateral Diffused Metal Oxide Semiconductor (LDMOS) is vulnerable to Single-Event Burnout (SEB) effect in the radiation environment, which is challenging for the design of high-voltage integrated circuit (HVIC). In this work, a Source-Segmented LDMOS (SS-LDMOS) structure for SEB hardness is proposed, which can reduce parasitic resistor and enhance hole discharge capacity nearby the source region. Through pulsed-laser experiments, the proposed devices are validated in two different high-voltage Bipolar-CMOS-DMOS (BCD) processes. Compared to conventional LDMOS, the SS-LDMOS can provide an improvement of SEB triggering voltage by 20.7% to 40%, without changing its electrical parameters such as threshold voltage, on-resistance, and breakdown voltage. Besides, the proposed approach has the advantage of zero additional mask, no additional processing step, and compact structure, in comparison with other existing hardness techniques. Therefore, it is promising in HVIC for aerospace applications.