Design and Implementation of a configurable Asynchronous Sample-Rate Converter for Digital Audio

Most of the modern SoC designs have multiple functional and processing blocks and all operating at different sampling rate, hence arises the need of sample rate converters. In digital-audio ASICs, it is very common to change the sampling rate by a factor (int or frac) to match a downstream block. This work mainly focuses on designing and implementing sample rate converters for conversions between arbitrary sample rates in between different blocks on a chip. The design of an ASRCs for digital-audio applications is presented here, which has a variable ratio based on the need. The sample rate of each block on-chip can be changed as per user choice as the ASRC is designed with configurable register controls.