Improving Threshold Voltage and Device Performance of Gate-First HfSiON/Metal Gate n-MOSFETs by an ALD La[sub 2]O[sub 3] Capping Layer

We have studied the effect on the electrical properties of depositing Lanthanum-oxide capping layers on Hafnium-silicon-oxynitride /Tantalum-silicon-nitride metal gate first stacks. The capping layers were deposited by atomic layer deposition (ALD) using a precursor and ozone. The capacitance voltage characteristics shifted negatively by a significant amount with increasing numbers of cycles, and the shifts in the flatband voltage with 10 ALD cycles were for gate stacks with compositions of 56 and 74%. An equivalent oxide thicknesses (EOT) of was obtained for the gate stack with composition of 74% with a capping layer. Postdeposition annealing at 1050°C caused Lanthanum diffusion into the gate stack, forming bonds at the interface, and increasing the dielectric constant. The threshold voltage achieved with two cycles and the 56% composition gate stack was , almost the same as that for /n-Poly Si devices. The drain current at improved dramatically with the increasing number of ALD cycles, with values twice as large for devices capped with compared to those with bare gate stacks (noncapped samples). The EOTs and gate leakage current densities clearly meet the criteria for half pitch metal gate bulk devices in the International Technology Roadmap for Semiconductor 2006.