All‐Solid‐State Ion Synaptic Transistor for Wafer‐Scale Integration with Electrolyte of a Nanoscale Thickness

Abstract Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with a large number of conductance levels is required. Here, an all‐solid‐state polymer electrolyte‐gated synaptic transistor (pEGST) is fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition process. The pEGST shows good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ pulse −1 . Selected 128 levels from 8,192 are used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7%.