Overcoming Design Challenges for High Bandwidth Memory Interface with CoWoS

High bandwidth memory (HBM) with Chip-onWafer-on-Substrate (CoWoS) packaging technology to achieve chiplet-based heterogeneous integration systems is increasingly adopted by the industry. Due to the number of IOs and micronscale structures, signal integrity analysis becomes challenging. This paper presents a novel EM solver with high capacity and scalability. An automated design flow is developed on top of the solver to facilitate the simulation of HBM interfaces for CoWoS. Various HBM interfaces are simulated for both CoWoS-R and CoWoS-S. Their performance is compared.