随时间变化的栅氧化层击穿
材料科学
MOSFET
沟槽
栅氧化层
光电子学
功率MOSFET
可靠性(半导体)
击穿电压
负偏压温度不稳定性
电气工程
平面的
碳化硅
阈值电压
介电强度
电压
电介质
功率(物理)
工程类
计算机科学
纳米技术
复合材料
物理
晶体管
计算机图形学(图像)
图层(电子)
量子力学
作者
Shengnan Zhu,Limeng Shi,Michael Jin,Jiashu Qian,Monikuntala Bhattacharya,Hema Lata Rao Maddi,Marvin H. White,Anant Agarwal,Tianshi Liu,Atsushi Shimbori,Chingchi Chen
标识
DOI:10.1109/irps48203.2023.10117998
摘要
The gate oxide reliability, bias temperature insta-bility (BTI), and short-circuit capability for commercial SiC power MOSFETs with planar and trench structures are evaluated and compared in this work. The asymmetric trench MOSFET has the thickest gate oxide among the tested devices, which provides the highest extrapolated gate oxide lifetime from the constant-voltage time-dependent dielectric breakdown (TDDB) measurements. Also, the asymmetric trench structure shows the longest short-circuit withstand time (SCWT) benefiting from the adjacent P+ regions. However, the asymmetric trench MOSFETs show a high threshold voltage shift during the BTI measurements under AC stress, indicating more at or near SiC/SiO 2 interface defects. The double trench MOSFETs also show better short-circuit ruggedness, but no obvious advantages in the TDDB measurements and BTI results.
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