Lv11
32 积分 2024-08-21 加入
A Fast automatic frequency calibration (AFC) scheme for phase-locked loop (PLL) frequency synthesizer
1小时前
待确认
A packaged 43-Gb/s clock and data recovery IC
1个月前
已完结
A 900-Mb/s CMOS data recovery DLL using half-frequency clock
1个月前
已完结
Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery
1个月前
已完结
A 52MHz And 155MHz Clock-recovery PLL
1个月前
已完结
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits
1个月前
已完结
具有减小的电流失配的电荷泵，可将PLL中的参考杂散最小化
1个月前
已完结
Low power D-latch design using MCML tri-state buffers
2个月前
已完结
MOS current mode circuits: analysis, design, and variability
2个月前
已完结
A 12.5Gbps dual loop quarter rate CDR using lock detecting technique in 55nm CMOS process
3个月前
已完结
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