A Hybrid Quenching and Active Reset Circuit for High-Speed SPAD Detectors

This paper presents a hybrid quenching and active reset circuit for high-speed single-photon avalanche diode (SPAD) detectors based on a standard 180 nm CMOS process. A hybrid quenching scheme combining cascaded passive quenching and variable-load quenching is employed to both reduce the response time of the front-end circuit from sensing the avalanche current to quenching it, and extend the quenching and recharging voltage range limited by the maximum allowable operation voltage of standard transistors. Simulation is performed based on a modified SPAD model built with Verilog-A language and ideal switches. Simulation results indicate that the sensing and quenching time is about 300 ps. Meanwhile, the quenching and reset voltage range provided by the front-end circuit is significantly improved from 1.8 V to 3 V. In addition, the hybrid quenching and active reset circuit is tunable, achieving a minimum dead time of about 2 ns.