Intra-field stress impact on global wafer deformation

One of the contributors to layer-to-layer overlay in today's chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane distortion patterns may be apparent after clamping. The wafer alignment system inside the scanner is designed to correct for these process-induced in-plane wafer distortion signatures. Depending on the complexity of the distortion pattern, the choice of wafer alignment model can be adapted to achieve the required overlay performance. While wafer overlay metrology is used to correct for the systematic part of the wafer distortion, the wafer alignment functionality addresses the random part that is varying from wafer-to-wafer. In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay performance down to the scanner baseline performance over the past years. In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However, since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and Logic.