A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where R ² maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps.